Unix Man page/Perldoc/Info page, English-Chinese Dictionary, Chinese-English Dictionary

make

File: make.info, Node: Top, Next: Overview, Prev: (dir), Up: (dir)

Make
****

The GNU `make' utility automatically determines which pieces of a
large program need to be recompiled, and issues the commands to
recompile them.

This edition of the `GNU Make Manual', last updated 08 July 2002,
documents GNU `make' Version 3.80.

This manual describes `make' and contains the following chapters:

* Menu:

* Overview:: Overview of `make'.
* Introduction:: An introduction to `make'.
* Makefiles:: Makefiles tell `make' what to do.
* Rules:: Rules describe when a file must be remade.
* Commands:: Commands say how to remake a file.
* Using Variables:: You can use variables to avoid repetition.
* Conditionals:: Use or ignore parts of the makefile based
on the values of variables.
* Functions:: Many powerful ways to manipulate text.
* Invoking make: Running. How to invoke `make' on the command line.
* Implicit Rules:: Use implicit rules to treat many files alike,
based on their file names.
* Archives:: How `make' can update library archives.
* Features:: Features GNU `make' has over other `make's.
* Missing:: What GNU `make' lacks from other `make's.
* Makefile Conventions:: Conventions for writing makefiles for
GNU programs.
* Quick Reference:: A quick reference for experienced users.
* Error Messages:: A list of common errors generated by `make'.
* Complex Makefile:: A real example of a straightforward,
but nontrivial, makefile.

* GNU Free Documentation License:: License for copying this manual
* Concept Index:: Index of Concepts
* Name Index:: Index of Functions, Variables, & Directives

--- The Detailed Node Listing ---

Overview of `make'

* Preparing:: Preparing and Running Make
* Reading:: On Reading this Text
* Bugs:: Problems and Bugs

An Introduction to Makefiles

* Rule Introduction:: What a rule looks like.
* Simple Makefile:: A Simple Makefile
* How Make Works:: How `make' Processes This Makefile
* Variables Simplify:: Variables Make Makefiles Simpler
* make Deduces:: Letting `make' Deduce the Commands
* Combine By Prerequisite:: Another Style of Makefile
* Cleanup:: Rules for Cleaning the Directory

Writing Makefiles

* Makefile Contents:: What makefiles contain.
* Makefile Names:: How to name your makefile.
* Include:: How one makefile can use another makefile.
* MAKEFILES Variable:: The environment can specify extra makefiles.
* MAKEFILE_LIST Variable:: Discover which makefiles have been read.
* Special Variables:: Other special variables.
* Remaking Makefiles:: How makefiles get remade.
* Overriding Makefiles:: How to override part of one makefile
with another makefile.
* Reading Makefiles:: How makefiles are parsed.

Writing Rules

* Rule Example:: An example explained.
* Rule Syntax:: General syntax explained.
* Prerequisite Types:: There are two types of prerequisites.
* Wildcards:: Using wildcard characters such as `*'.
* Directory Search:: Searching other directories for source files.
* Phony Targets:: Using a target that is not a real file's name.
* Force Targets:: You can use a target without commands
or prerequisites to mark other
targets as phony.
* Empty Targets:: When only the date matters and the
files are empty.
* Special Targets:: Targets with special built-in meanings.
* Multiple Targets:: When to make use of several targets in a rule.
* Multiple Rules:: How to use several rules with the same target.
* Static Pattern:: Static pattern rules apply to multiple targets
and can vary the prerequisites according to
the target name.
* Double-Colon:: How to use a special kind of rule to allow
several independent rules for one target.
* Automatic Prerequisites:: How to automatically generate rules giving
prerequisites from source files themselves.

Using Wildcard Characters in File Names

* Wildcard Examples:: Several examples
* Wildcard Pitfall:: Problems to avoid.
* Wildcard Function:: How to cause wildcard expansion where
it does not normally take place.

Searching Directories for Prerequisites

* General Search:: Specifying a search path that applies
to every prerequisite.
* Selective Search:: Specifying a search path
for a specified class of names.
* Search Algorithm:: When and how search paths are applied.
* Commands/Search:: How to write shell commands that work together
with search paths.
* Implicit/Search:: How search paths affect implicit rules.
* Libraries/Search:: Directory search for link libraries.

Static Pattern Rules

* Static Usage:: The syntax of static pattern rules.
* Static versus Implicit:: When are they better than implicit rules?

Writing the Commands in Rules

* Echoing:: How to control when commands are echoed.
* Execution:: How commands are executed.
* Parallel:: How commands can be executed in parallel.
* Errors:: What happens after a command execution error.
* Interrupts:: What happens when a command is interrupted.
* Recursion:: Invoking `make' from makefiles.
* Sequences:: Defining canned sequences of commands.
* Empty Commands:: Defining useful, do-nothing commands.

Recursive Use of `make'

* MAKE Variable:: The special effects of using `$(MAKE)'.
* Variables/Recursion:: How to communicate variables to a sub-`make'.
* Options/Recursion:: How to communicate options to a sub-`make'.
* -w Option:: How the `-w' or `--print-directory' option
helps debug use of recursive `make' commands.

How to Use Variables

* Reference:: How to use the value of a variable.
* Flavors:: Variables come in two flavors.
* Advanced:: Advanced features for referencing a variable.
* Values:: All the ways variables get their values.
* Setting:: How to set a variable in the makefile.
* Appending:: How to append more text to the old value
of a variable.
* Override Directive:: How to set a variable in the makefile even if
the user has set it with a command argument.
* Defining:: An alternate way to set a variable
to a verbatim string.
* Environment:: Variable values can come from the environment.
* Target-specific:: Variable values can be defined on a per-target
basis.
* Pattern-specific:: Target-specific variable values can be applied
to a group of targets that match a pattern.

Advanced Features for Reference to Variables

* Substitution Refs:: Referencing a variable with
substitutions on the value.
* Computed Names:: Computing the name of the variable to refer to.

Conditional Parts of Makefiles

* Conditional Example:: Example of a conditional
* Conditional Syntax:: The syntax of conditionals.
* Testing Flags:: Conditionals that test flags.

Functions for Transforming Text

* Syntax of Functions:: How to write a function call.
* Text Functions:: General-purpose text manipulation functions.
* File Name Functions:: Functions for manipulating file names.
* Foreach Function:: Repeat some text with controlled variation.
* If Function:: Conditionally expand a value.
* Call Function:: Expand a user-defined function.
* Value Function:: Return the un-expanded value of a variable.
* Eval Function:: Evaluate the arguments as makefile syntax.
* Origin Function:: Find where a variable got its value.
* Shell Function:: Substitute the output of a shell command.
* Make Control Functions:: Functions that control how make runs.

How to Run `make'

* Makefile Arguments:: How to specify which makefile to use.
* Goals:: How to use goal arguments to specify which
parts of the makefile to use.
* Instead of Execution:: How to use mode flags to specify what
kind of thing to do with the commands
in the makefile other than simply
execute them.
* Avoiding Compilation:: How to avoid recompiling certain files.
* Overriding:: How to override a variable to specify
an alternate compiler and other things.
* Testing:: How to proceed past some errors, to
test compilation.
* Options Summary:: Summary of Options

Using Implicit Rules

* Using Implicit:: How to use an existing implicit rule
to get the commands for updating a file.
* Catalogue of Rules:: A list of built-in implicit rules.
* Implicit Variables:: How to change what predefined rules do.
* Chained Rules:: How to use a chain of implicit rules.
* Pattern Rules:: How to define new implicit rules.
* Last Resort:: How to defining commands for rules
which cannot find any.
* Suffix Rules:: The old-fashioned style of implicit rule.
* Implicit Rule Search:: The precise algorithm for applying
implicit rules.

Defining and Redefining Pattern Rules

* Pattern Intro:: An introduction to pattern rules.
* Pattern Examples:: Examples of pattern rules.
* Automatic:: How to use automatic variables in the
commands of implicit rules.
* Pattern Match:: How patterns match.
* Match-Anything Rules:: Precautions you should take prior to
defining rules that can match any
target file whatever.
* Canceling Rules:: How to override or cancel built-in rules.

Using `make' to Update Archive Files

* Archive Members:: Archive members as targets.
* Archive Update:: The implicit rule for archive member targets.
* Archive Pitfalls:: Dangers to watch out for when using archives.
* Archive Suffix Rules:: You can write a special kind of suffix rule
for updating archives.

Implicit Rule for Archive Member Targets

* Archive Symbols:: How to update archive symbol directories.

Makefile Conventions

* Makefile Basics:: General Conventions for Makefiles
* Utilities in Makefiles:: Utilities in Makefiles
* Command Variables:: Variables for Specifying Commands
* Directory Variables:: Variables for Installation Directories
* Standard Targets:: Standard Targets for Users
* Install Command Categories:: Three categories of commands in the `install'

Copying This Manual

File: make.info, Node: Overview, Next: Introduction, Prev: Top, Up: Top

Overview of `make'
******************

The `make' utility automatically determines which pieces of a large
program need to be recompiled, and issues commands to recompile them.
This manual describes GNU `make', which was implemented by Richard
Stallman and Roland McGrath. Development since Version 3.76 has been
handled by Paul Smith.

GNU `make' conforms to section 6.2 of `IEEE Standard 1003.2-1992'
(POSIX.2).

Our examples show C programs, since they are most common, but you
can use `make' with any programming language whose compiler can be run
with a shell command. Indeed, `make' is not limited to programs. You
can use it to describe any task where some files must be updated
automatically from others whenever the others change.

* Menu:

* Preparing:: Preparing and Running Make
* Reading:: On Reading this Text
* Bugs:: Problems and Bugs

File: make.info, Node: Preparing, Next: Reading, Prev: Overview, Up: Overview

Preparing and Running Make
==========================

To prepare to use `make', you must write a file called the
"makefile" that describes the relationships among files in your program
and provides commands for updating each file. In a program, typically,
the executable file is updated from object files, which are in turn
made by compiling source files.

Once a suitable makefile exists, each time you change some source
files, this simple shell command:

make

suffices to perform all necessary recompilations. The `make' program
uses the makefile data base and the last-modification times of the
files to decide which of the files need to be updated. For each of
those files, it issues the commands recorded in the data base.

You can provide command line arguments to `make' to control which
files should be recompiled, or how. *Note How to Run `make': Running.

File: make.info, Node: Reading, Next: Bugs, Prev: Preparing, Up: Overview

How to Read This Manual
=======================

If you are new to `make', or are looking for a general introduction,
read the first few sections of each chapter, skipping the later
sections. In each chapter, the first few sections contain introductory
or general information and the later sections contain specialized or
technical information. The exception is the second chapter, *Note An
Introduction to Makefiles: Introduction, all of which is introductory.

If you are familiar with other `make' programs, see *Note Features
of GNU `make': Features, which lists the enhancements GNU `make' has,
and *Note Incompatibilities and Missing Features: Missing, which
explains the few things GNU `make' lacks that others have.

For a quick summary, see *Note Options Summary::, *Note Quick
Reference::, and *Note Special Targets::.

File: make.info, Node: Bugs, Prev: Reading, Up: Overview

Problems and Bugs
=================

If you have problems with GNU `make' or think you've found a bug,
please report it to the developers; we cannot promise to do anything but
we might well want to fix it.

Before reporting a bug, make sure you've actually found a real bug.
Carefully reread the documentation and see if it really says you can do
what you're trying to do. If it's not clear whether you should be able
to do something or not, report that too; it's a bug in the
documentation!

Before reporting a bug or trying to fix it yourself, try to isolate
it to the smallest possible makefile that reproduces the problem. Then
send us the makefile and the exact results `make' gave you, including
any error or warning messages. Please don't paraphrase these messages:
it's best to cut and paste them into your report. When generating this
small makefile, be sure to not use any non-free or unusual tools in
your commands: you can almost always emulate what such a tool would do
with simple shell commands. Finally, be sure to explain what you
expected to occur; this will help us decide whether the problem was
really in the documentation.

Once you have a precise problem you can report it in one of two ways.
Either send electronic mail to:

bug-make AT gnu.org

or use our Web-based project management tool, at:

http://savannah.gnu.org/projects/make/

In addition to the information above, please be careful to include the
version number of `make' you are using. You can get this information
with the command `make --version'. Be sure also to include the type of
machine and operating system you are using. One way to obtain this
information is by looking at the final lines of output from the command
`make --help'.

File: make.info, Node: Introduction, Next: Makefiles, Prev: Overview, Up: Top

An Introduction to Makefiles
****************************

You need a file called a "makefile" to tell `make' what to do. Most
often, the makefile tells `make' how to compile and link a program.

In this chapter, we will discuss a simple makefile that describes
how to compile and link a text editor which consists of eight C source
files and three header files. The makefile can also tell `make' how to
run miscellaneous commands when explicitly asked (for example, to remove
certain files as a clean-up operation). To see a more complex example
of a makefile, see *Note Complex Makefile::.

When `make' recompiles the editor, each changed C source file must
be recompiled. If a header file has changed, each C source file that
includes the header file must be recompiled to be safe. Each
compilation produces an object file corresponding to the source file.
Finally, if any source file has been recompiled, all the object files,
whether newly made or saved from previous compilations, must be linked
together to produce the new executable editor.

* Menu:

File: make.info, Node: Rule Introduction, Next: Simple Makefile, Prev: Introduction, Up: Introduction

What a Rule Looks Like
======================

A simple makefile consists of "rules" with the following shape:

TARGET ... : PREREQUISITES ...
COMMAND
...
...

A "target" is usually the name of a file that is generated by a
program; examples of targets are executable or object files. A target
can also be the name of an action to carry out, such as `clean' (*note
Phony Targets::).

A "prerequisite" is a file that is used as input to create the
target. A target often depends on several files.

A "command" is an action that `make' carries out. A rule may have
more than one command, each on its own line. *Please note:* you need
to put a tab character at the beginning of every command line! This is
an obscurity that catches the unwary.

Usually a command is in a rule with prerequisites and serves to
create a target file if any of the prerequisites change. However, the
rule that specifies commands for the target need not have
prerequisites. For example, the rule containing the delete command
associated with the target `clean' does not have prerequisites.

A "rule", then, explains how and when to remake certain files which
are the targets of the particular rule. `make' carries out the
commands on the prerequisites to create or update the target. A rule
can also explain how and when to carry out an action. *Note Writing
Rules: Rules.

A makefile may contain other text besides rules, but a simple
makefile need only contain rules. Rules may look somewhat more
complicated than shown in this template, but all fit the pattern more
or less.

File: make.info, Node: Simple Makefile, Next: How Make Works, Prev: Rule Introduction, Up: Introduction

A Simple Makefile
=================

Here is a straightforward makefile that describes the way an
executable file called `edit' depends on eight object files which, in
turn, depend on eight C source and three header files.

In this example, all the C files include `defs.h', but only those
defining editing commands include `command.h', and only low level files
that change the editor buffer include `buffer.h'.

edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
cc -o edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

We split each long line into two lines using backslash-newline; this is
like using one long line, but is easier to read.

To use this makefile to create the executable file called `edit',
type:

make

To use this makefile to delete the executable file and all the object
files from the directory, type:

make clean

In the example makefile, the targets include the executable file
`edit', and the object files `main.o' and `kbd.o'. The prerequisites
are files such as `main.c' and `defs.h'. In fact, each `.o' file is
both a target and a prerequisite. Commands include `cc -c main.c' and
`cc -c kbd.c'.

When a target is a file, it needs to be recompiled or relinked if any
of its prerequisites change. In addition, any prerequisites that are
themselves automatically generated should be updated first. In this
example, `edit' depends on each of the eight object files; the object
file `main.o' depends on the source file `main.c' and on the header
file `defs.h'.

A shell command follows each line that contains a target and
prerequisites. These shell commands say how to update the target file.
A tab character must come at the beginning of every command line to
distinguish commands lines from other lines in the makefile. (Bear in
mind that `make' does not know anything about how the commands work.
It is up to you to supply commands that will update the target file
properly. All `make' does is execute the commands in the rule you have
specified when the target file needs to be updated.)

The target `clean' is not a file, but merely the name of an action.
Since you normally do not want to carry out the actions in this rule,
`clean' is not a prerequisite of any other rule. Consequently, `make'
never does anything with it unless you tell it specifically. Note that
this rule not only is not a prerequisite, it also does not have any
prerequisites, so the only purpose of the rule is to run the specified
commands. Targets that do not refer to files but are just actions are
called "phony targets". *Note Phony Targets::, for information about
this kind of target. *Note Errors in Commands: Errors, to see how to
cause `make' to ignore errors from `rm' or any other command.

File: make.info, Node: How Make Works, Next: Variables Simplify, Prev: Simple Makefile, Up: Introduction

How `make' Processes a Makefile
===============================

By default, `make' starts with the first target (not targets whose
names start with `.'). This is called the "default goal". ("Goals"
are the targets that `make' strives ultimately to update. *Note
Arguments to Specify the Goals: Goals.)

In the simple example of the previous section, the default goal is to
update the executable program `edit'; therefore, we put that rule first.

Thus, when you give the command:

make

`make' reads the makefile in the current directory and begins by
processing the first rule. In the example, this rule is for relinking
`edit'; but before `make' can fully process this rule, it must process
the rules for the files that `edit' depends on, which in this case are
the object files. Each of these files is processed according to its
own rule. These rules say to update each `.o' file by compiling its
source file. The recompilation must be done if the source file, or any
of the header files named as prerequisites, is more recent than the
object file, or if the object file does not exist.

The other rules are processed because their targets appear as
prerequisites of the goal. If some other rule is not depended on by the
goal (or anything it depends on, etc.), that rule is not processed,
unless you tell `make' to do so (with a command such as `make clean').

Before recompiling an object file, `make' considers updating its
prerequisites, the source file and header files. This makefile does not
specify anything to be done for them--the `.c' and `.h' files are not
the targets of any rules--so `make' does nothing for these files. But
`make' would update automatically generated C programs, such as those
made by Bison or Yacc, by their own rules at this time.

After recompiling whichever object files need it, `make' decides
whether to relink `edit'. This must be done if the file `edit' does
not exist, or if any of the object files are newer than it. If an
object file was just recompiled, it is now newer than `edit', so `edit'
is relinked.

Thus, if we change the file `insert.c' and run `make', `make' will
compile that file to update `insert.o', and then link `edit'. If we
change the file `command.h' and run `make', `make' will recompile the
object files `kbd.o', `command.o' and `files.o' and then link the file
`edit'.

File: make.info, Node: Variables Simplify, Next: make Deduces, Prev: How Make Works, Up: Introduction

Variables Make Makefiles Simpler
================================

In our example, we had to list all the object files twice in the
rule for `edit' (repeated here):

edit : main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
cc -o edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

Such duplication is error-prone; if a new object file is added to the
system, we might add it to one list and forget the other. We can
eliminate the risk and simplify the makefile by using a variable.
"Variables" allow a text string to be defined once and substituted in
multiple places later (*note How to Use Variables: Using Variables.).

It is standard practice for every makefile to have a variable named
`objects', `OBJECTS', `objs', `OBJS', `obj', or `OBJ' which is a list
of all object file names. We would define such a variable `objects'
with a line like this in the makefile:

objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

Then, each place we want to put a list of the object file names, we can
substitute the variable's value by writing `$(objects)' (*note How to
Use Variables: Using Variables.).

Here is how the complete simple makefile looks when you use a
variable for the object files:

objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit $(objects)

File: make.info, Node: make Deduces, Next: Combine By Prerequisite, Prev: Variables Simplify, Up: Introduction

Letting `make' Deduce the Commands
==================================

It is not necessary to spell out the commands for compiling the
individual C source files, because `make' can figure them out: it has an
"implicit rule" for updating a `.o' file from a correspondingly named
`.c' file using a `cc -c' command. For example, it will use the
command `cc -c main.c -o main.o' to compile `main.c' into `main.o'. We
can therefore omit the commands from the rules for the object files.
*Note Using Implicit Rules: Implicit Rules.

When a `.c' file is used automatically in this way, it is also
automatically added to the list of prerequisites. We can therefore omit
the `.c' files from the prerequisites, provided we omit the commands.

Here is the entire example, with both of these changes, and a
variable `objects' as suggested above:

objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY : clean
clean :
rm edit $(objects)

This is how we would write the makefile in actual practice. (The
complications associated with `clean' are described elsewhere. See
*Note Phony Targets::, and *Note Errors in Commands: Errors.)

Because implicit rules are so convenient, they are important. You
will see them used frequently.

File: make.info, Node: Combine By Prerequisite, Next: Cleanup, Prev: make Deduces, Up: Introduction

Another Style of Makefile
=========================

When the objects of a makefile are created only by implicit rules, an
alternative style of makefile is possible. In this style of makefile,
you group entries by their prerequisites instead of by their targets.
Here is what one looks like:

objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)

$(objects) : defs.h
kbd.o command.o files.o : command.h
display.o insert.o search.o files.o : buffer.h

Here `defs.h' is given as a prerequisite of all the object files;
`command.h' and `buffer.h' are prerequisites of the specific object
files listed for them.

Whether this is better is a matter of taste: it is more compact, but
some people dislike it because they find it clearer to put all the
information about each target in one place.

File: make.info, Node: Cleanup, Prev: Combine By Prerequisite, Up: Introduction

Rules for Cleaning the Directory
================================

Compiling a program is not the only thing you might want to write
rules for. Makefiles commonly tell how to do a few other things besides
compiling a program: for example, how to delete all the object files
and executables so that the directory is `clean'.

Here is how we could write a `make' rule for cleaning our example
editor:

clean:
rm edit $(objects)

In practice, we might want to write the rule in a somewhat more
complicated manner to handle unanticipated situations. We would do
this:

.PHONY : clean
clean :
-rm edit $(objects)

This prevents `make' from getting confused by an actual file called
`clean' and causes it to continue in spite of errors from `rm'. (See
*Note Phony Targets::, and *Note Errors in Commands: Errors.)

A rule such as this should not be placed at the beginning of the
makefile, because we do not want it to run by default! Thus, in the
example makefile, we want the rule for `edit', which recompiles the
editor, to remain the default goal.

Since `clean' is not a prerequisite of `edit', this rule will not
run at all if we give the command `make' with no arguments. In order
to make the rule run, we have to type `make clean'. *Note How to Run
`make': Running.

File: make.info, Node: Makefiles, Next: Rules, Prev: Introduction, Up: Top

Writing Makefiles
*****************

The information that tells `make' how to recompile a system comes
from reading a data base called the "makefile".

* Menu:

File: make.info, Node: Makefile Contents, Next: Makefile Names, Prev: Makefiles, Up: Makefiles

What Makefiles Contain
======================

Makefiles contain five kinds of things: "explicit rules", "implicit
rules", "variable definitions", "directives", and "comments". Rules,
variables, and directives are described at length in later chapters.

* An "explicit rule" says when and how to remake one or more files,
called the rule's targets. It lists the other files that the
targets depend on, call the "prerequisites" of the target, and may
also give commands to use to create or update the targets. *Note
Writing Rules: Rules.

* An "implicit rule" says when and how to remake a class of files
based on their names. It describes how a target may depend on a
file with a name similar to the target and gives commands to
create or update such a target. *Note Using Implicit Rules:
Implicit Rules.

* A "variable definition" is a line that specifies a text string
value for a variable that can be substituted into the text later.
The simple makefile example shows a variable definition for
`objects' as a list of all object files (*note Variables Make
Makefiles Simpler: Variables Simplify.).

* A "directive" is a command for `make' to do something special while
reading the makefile. These include:

* Reading another makefile (*note Including Other Makefiles:
Include.).

* Deciding (based on the values of variables) whether to use or
ignore a part of the makefile (*note Conditional Parts of
Makefiles: Conditionals.).

* Defining a variable from a verbatim string containing
multiple lines (*note Defining Variables Verbatim: Defining.).

* `#' in a line of a makefile starts a "comment". It and the rest
of the line are ignored, except that a trailing backslash not
escaped by another backslash will continue the comment across
multiple lines. A line containing just a comment (with perhaps
spaces before it) is effectively blank, and is ignored. If you
want a literal `#', escape it with a backslash (e.g., `\#').
Comments may appear on any line in the makefile, although they are
treated specially in certain situations.

Within a command script (if the line begins with a TAB character)
the entire line is passed to the shell, just as with any other
line that begins with a TAB. The shell decides how to interpret
the text: whether or not this is a comment is up to the shell.

Within a `define' directive, comments are not ignored during the
definition of the variable, but rather kept intact in the value of
the variable. When the variable is expanded they will either be
treated as `make' comments or as command script text, depending on
the context in which the variable is evaluated.

File: make.info, Node: Makefile Names, Next: Include, Prev: Makefile Contents, Up: Makefiles

What Name to Give Your Makefile
===============================

By default, when `make' looks for the makefile, it tries the
following names, in order: `GNUmakefile', `makefile' and `Makefile'.

Normally you should call your makefile either `makefile' or
`Makefile'. (We recommend `Makefile' because it appears prominently
near the beginning of a directory listing, right near other important
files such as `README'.) The first name checked, `GNUmakefile', is not
recommended for most makefiles. You should use this name if you have a
makefile that is specific to GNU `make', and will not be understood by
other versions of `make'. Other `make' programs look for `makefile' and
`Makefile', but not `GNUmakefile'.

If `make' finds none of these names, it does not use any makefile.
Then you must specify a goal with a command argument, and `make' will
attempt to figure out how to remake it using only its built-in implicit
rules. *Note Using Implicit Rules: Implicit Rules.

If you want to use a nonstandard name for your makefile, you can
specify the makefile name with the `-f' or `--file' option. The
arguments `-f NAME' or `--file=NAME' tell `make' to read the file NAME
as the makefile. If you use more than one `-f' or `--file' option, you
can specify several makefiles. All the makefiles are effectively
concatenated in the order specified. The default makefile names
`GNUmakefile', `makefile' and `Makefile' are not checked automatically
if you specify `-f' or `--file'.

File: make.info, Node: Include, Next: MAKEFILES Variable, Prev: Makefile Names, Up: Makefiles

Including Other Makefiles
=========================

The `include' directive tells `make' to suspend reading the current
makefile and read one or more other makefiles before continuing. The
directive is a line in the makefile that looks like this:

include FILENAMES...

FILENAMES can contain shell file name patterns.

Extra spaces are allowed and ignored at the beginning of the line,
but a tab is not allowed. (If the line begins with a tab, it will be
considered a command line.) Whitespace is required between `include'
and the file names, and between file names; extra whitespace is ignored
there and at the end of the directive. A comment starting with `#' is
allowed at the end of the line. If the file names contain any variable
or function references, they are expanded. *Note How to Use Variables:
Using Variables.

For example, if you have three `.mk' files, `a.mk', `b.mk', and
`c.mk', and `$(bar)' expands to `bish bash', then the following
expression

include foo *.mk $(bar)

is equivalent to

include foo a.mk b.mk c.mk bish bash

When `make' processes an `include' directive, it suspends reading of
the containing makefile and reads from each listed file in turn. When
that is finished, `make' resumes reading the makefile in which the
directive appears.

One occasion for using `include' directives is when several programs,
handled by individual makefiles in various directories, need to use a
common set of variable definitions (*note Setting Variables: Setting.)
or pattern rules (*note Defining and Redefining Pattern Rules: Pattern
Rules.).

Another such occasion is when you want to generate prerequisites from
source files automatically; the prerequisites can be put in a file that
is included by the main makefile. This practice is generally cleaner
than that of somehow appending the prerequisites to the end of the main
makefile as has been traditionally done with other versions of `make'.
*Note Automatic Prerequisites::.

If the specified name does not start with a slash, and the file is
not found in the current directory, several other directories are
searched. First, any directories you have specified with the `-I' or
`--include-dir' option are searched (*note Summary of Options: Options
Summary.). Then the following directories (if they exist) are
searched, in this order: `PREFIX/include' (normally `/usr/local/include'
(1)) `/usr/gnu/include', `/usr/local/include', `/usr/include'.

If an included makefile cannot be found in any of these directories,
a warning message is generated, but it is not an immediately fatal
error; processing of the makefile containing the `include' continues.
Once it has finished reading makefiles, `make' will try to remake any
that are out of date or don't exist. *Note How Makefiles Are Remade:
Remaking Makefiles. Only after it has tried to find a way to remake a
makefile and failed, will `make' diagnose the missing makefile as a
fatal error.

If you want `make' to simply ignore a makefile which does not exist
and cannot be remade, with no error message, use the `-include'
directive instead of `include', like this:

-include FILENAMES...

This acts like `include' in every way except that there is no error
(not even a warning) if any of the FILENAMES do not exist. For
compatibility with some other `make' implementations, `sinclude' is
another name for `-include'.

---------- Footnotes ----------

(1) GNU Make compiled for MS-DOS and MS-Windows behaves as if PREFIX
has been defined to be the root of the DJGPP tree hierarchy.

File: make.info, Node: MAKEFILES Variable, Next: MAKEFILE_LIST Variable, Prev: Include, Up: Makefiles

The Variable `MAKEFILES'
========================

If the environment variable `MAKEFILES' is defined, `make' considers
its value as a list of names (separated by whitespace) of additional
makefiles to be read before the others. This works much like the
`include' directive: various directories are searched for those files
(*note Including Other Makefiles: Include.). In addition, the default
goal is never taken from one of these makefiles and it is not an error
if the files listed in `MAKEFILES' are not found.

The main use of `MAKEFILES' is in communication between recursive
invocations of `make' (*note Recursive Use of `make': Recursion.). It
usually is not desirable to set the environment variable before a
top-level invocation of `make', because it is usually better not to
mess with a makefile from outside. However, if you are running `make'
without a specific makefile, a makefile in `MAKEFILES' can do useful
things to help the built-in implicit rules work better, such as
defining search paths (*note Directory Search::).

Some users are tempted to set `MAKEFILES' in the environment
automatically on login, and program makefiles to expect this to be done.
This is a very bad idea, because such makefiles will fail to work if
run by anyone else. It is much better to write explicit `include'
directives in the makefiles. *Note Including Other Makefiles: Include.

File: make.info, Node: MAKEFILE_LIST Variable, Next: Special Variables, Prev: MAKEFILES Variable, Up: Makefiles

The Variable `MAKEFILE_LIST'
============================

As `make' reads various makefiles, including any obtained from the
`MAKEFILES' variable, the command line, the default files, or from
`include' directives, their names will be automatically appended to the
`MAKEFILE_LIST' variable. They are added right before `make' begins to
parse them.

This means that if the first thing a makefile does is examine the
last word in this variable, it will be the name of the current makefile.
Once the current makefile has used `include', however, the last word
will be the just-included makefile.

If a makefile named `Makefile' has this content:

name1 := $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))

include inc.mk

name2 := $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))

all:
@echo name1 = $(name1)
@echo name2 = $(name2)

then you would expect to see this output:

name1 = Makefile
name2 = inc.mk

*Note Text Functions::, for more information on the `word' and
`words' functions used above. *Note The Two Flavors of Variables:
Flavors, for more information on simply-expanded (`:=') variable
definitions.

File: make.info, Node: Special Variables, Next: Remaking Makefiles, Prev: MAKEFILE_LIST Variable, Up: Makefiles

Other Special Variables
=======================

GNU `make' also supports a special variable. Note that any value
you assign to this variable will be ignored; it will always return its
special value.

The first special variable is `.VARIABLES'. When expanded, the
value consists of a list of the _names_ of all global variables defined
in all makefiles read up until that point. This includes variables
which have empty values, as well as built-in variables (*note Variables
Used by Implicit Rules: Implicit Variables.), but does not include any
variables which are only defined in a target-specific context.

File: make.info, Node: Remaking Makefiles, Next: Overriding Makefiles, Prev: Special Variables, Up: Makefiles

How Makefiles Are Remade
========================

Sometimes makefiles can be remade from other files, such as RCS or
SCCS files. If a makefile can be remade from other files, you probably
want `make' to get an up-to-date version of the makefile to read in.

To this end, after reading in all makefiles, `make' will consider
each as a goal target and attempt to update it. If a makefile has a
rule which says how to update it (found either in that very makefile or
in another one) or if an implicit rule applies to it (*note Using
Implicit Rules: Implicit Rules.), it will be updated if necessary.
After all makefiles have been checked, if any have actually been
changed, `make' starts with a clean slate and reads all the makefiles
over again. (It will also attempt to update each of them over again,
but normally this will not change them again, since they are already up
to date.)

If you know that one or more of your makefiles cannot be remade and
you want to keep `make' from performing an implicit rule search on
them, perhaps for efficiency reasons, you can use any normal method of
preventing implicit rule lookup to do so. For example, you can write an
explicit rule with the makefile as the target, and an empty command
string (*note Using Empty Commands: Empty Commands.).

If the makefiles specify a double-colon rule to remake a file with
commands but no prerequisites, that file will always be remade (*note
Double-Colon::). In the case of makefiles, a makefile that has a
double-colon rule with commands but no prerequisites will be remade
every time `make' is run, and then again after `make' starts over and
reads the makefiles in again. This would cause an infinite loop:
`make' would constantly remake the makefile, and never do anything
else. So, to avoid this, `make' will *not* attempt to remake makefiles
which are specified as targets of a double-colon rule with commands but
no prerequisites.

If you do not specify any makefiles to be read with `-f' or `--file'
options, `make' will try the default makefile names; *note What Name to
Give Your Makefile: Makefile Names.. Unlike makefiles explicitly
requested with `-f' or `--file' options, `make' is not certain that
these makefiles should exist. However, if a default makefile does not
exist but can be created by running `make' rules, you probably want the
rules to be run so that the makefile can be used.

Therefore, if none of the default makefiles exists, `make' will try
to make each of them in the same order in which they are searched for
(*note What Name to Give Your Makefile: Makefile Names.) until it
succeeds in making one, or it runs out of names to try. Note that it
is not an error if `make' cannot find or make any makefile; a makefile
is not always necessary.

When you use the `-t' or `--touch' option (*note Instead of
Executing the Commands: Instead of Execution.), you would not want to
use an out-of-date makefile to decide which targets to touch. So the
`-t' option has no effect on updating makefiles; they are really
updated even if `-t' is specified. Likewise, `-q' (or `--question')
and `-n' (or `--just-print') do not prevent updating of makefiles,
because an out-of-date makefile would result in the wrong output for
other targets. Thus, `make -f mfile -n foo' will update `mfile', read
it in, and then print the commands to update `foo' and its prerequisites
without running them. The commands printed for `foo' will be those
specified in the updated contents of `mfile'.

However, on occasion you might actually wish to prevent updating of
even the makefiles. You can do this by specifying the makefiles as
goals in the command line as well as specifying them as makefiles.
When the makefile name is specified explicitly as a goal, the options
`-t' and so on do apply to them.

Thus, `make -f mfile -n mfile foo' would read the makefile `mfile',
print the commands needed to update it without actually running them,
and then print the commands needed to update `foo' without running
them. The commands for `foo' will be those specified by the existing
contents of `mfile'.

File: make.info, Node: Overriding Makefiles, Next: Reading Makefiles, Prev: Remaking Makefiles, Up: Makefiles

Overriding Part of Another Makefile
===================================

Sometimes it is useful to have a makefile that is mostly just like
another makefile. You can often use the `include' directive to include
one in the other, and add more targets or variable definitions.
However, if the two makefiles give different commands for the same
target, `make' will not let you just do this. But there is another way.

In the containing makefile (the one that wants to include the other),
you can use a match-anything pattern rule to say that to remake any
target that cannot be made from the information in the containing
makefile, `make' should look in another makefile. *Note Pattern
Rules::, for more information on pattern rules.

For example, if you have a makefile called `Makefile' that says how
to make the target `foo' (and other targets), you can write a makefile
called `GNUmakefile' that contains:

foo:
frobnicate > foo

%: force
@$(MAKE) -f Makefile $@
force: ;

If you say `make foo', `make' will find `GNUmakefile', read it, and
see that to make `foo', it needs to run the command `frobnicate > foo'.
If you say `make bar', `make' will find no way to make `bar' in
`GNUmakefile', so it will use the commands from the pattern rule: `make
-f Makefile bar'. If `Makefile' provides a rule for updating `bar',
`make' will apply the rule. And likewise for any other target that
`GNUmakefile' does not say how to make.

The way this works is that the pattern rule has a pattern of just
`%', so it matches any target whatever. The rule specifies a
prerequisite `force', to guarantee that the commands will be run even
if the target file already exists. We give `force' target empty
commands to prevent `make' from searching for an implicit rule to build
it--otherwise it would apply the same match-anything rule to `force'
itself and create a prerequisite loop!

File: make.info, Node: Reading Makefiles, Prev: Overriding Makefiles, Up: Makefiles

How `make' Reads a Makefile
===========================

GNU `make' does its work in two distinct phases. During the first
phase it reads all the makefiles, included makefiles, etc. and
internalizes all the variables and their values, implicit and explicit
rules, and constructs a dependency graph of all the targets and their
prerequisites. During the second phase, `make' uses these internal
structures to determine what targets will need to be rebuilt and to
invoke the rules necessary to do so.

It's important to understand this two-phase approach because it has a
direct impact on how variable and function expansion happens; this is
often a source of some confusion when writing makefiles. Here we will
present a summary of the phases in which expansion happens for different
constructs within the makefile. We say that expansion is "immediate"
if it happens during the first phase: in this case `make' will expand
any variables or functions in that section of a construct as the
makefile is parsed. We say that expansion is "deferred" if expansion
is not performed immediately. Expansion of deferred construct is not
performed until either the construct appears later in an immediate
context, or until the second phase.

You may not be familiar with some of these constructs yet. You can
reference this section as you become familiar with them, in later
chapters.

Variable Assignment
-------------------

Variable definitions are parsed as follows:

IMMEDIATE = DEFERRED
IMMEDIATE ?= DEFERRED
IMMEDIATE := IMMEDIATE
IMMEDIATE += DEFERRED or IMMEDIATE

define IMMEDIATE
DEFERRED
endef

For the append operator, `+=', the right-hand side is considered
immediate if the variable was previously set as a simple variable
(`:='), and deferred otherwise.

Conditional Statements
----------------------

All instances of conditional syntax are parsed immediately, in their
entirety; this includes the `ifdef', `ifeq', `ifndef', and `ifneq'
forms.

Rule Definition
---------------

A rule is always expanded the same way, regardless of the form:

IMMEDIATE : IMMEDIATE ; DEFERRED
DEFERRED

That is, the target and prerequisite sections are expanded
immediately, and the commands used to construct the target are always
deferred. This general rule is true for explicit rules, pattern rules,
suffix rules, static pattern rules, and simple prerequisite definitions.

File: make.info, Node: Rules, Next: Commands, Prev: Makefiles, Up: Top

Writing Rules
*************

A "rule" appears in the makefile and says when and how to remake
certain files, called the rule's "targets" (most often only one per
rule). It lists the other files that are the "prerequisites" of the
target, and "commands" to use to create or update the target.

The order of rules is not significant, except for determining the
"default goal": the target for `make' to consider, if you do not
otherwise specify one. The default goal is the target of the first
rule in the first makefile. If the first rule has multiple targets,
only the first target is taken as the default. There are two
exceptions: a target starting with a period is not a default unless it
contains one or more slashes, `/', as well; and, a target that defines
a pattern rule has no effect on the default goal. (*Note Defining and
Redefining Pattern Rules: Pattern Rules.)

Therefore, we usually write the makefile so that the first rule is
the one for compiling the entire program or all the programs described
by the makefile (often with a target called `all'). *Note Arguments to
Specify the Goals: Goals.

* Menu:

File: make.info, Node: Rule Example, Next: Rule Syntax, Prev: Rules, Up: Rules

Rule Example
============

Here is an example of a rule:

foo.o : foo.c defs.h # module for twiddling the frobs
cc -c -g foo.c

Its target is `foo.o' and its prerequisites are `foo.c' and
`defs.h'. It has one command, which is `cc -c -g foo.c'. The command
line starts with a tab to identify it as a command.

This rule says two things:

* How to decide whether `foo.o' is out of date: it is out of date if
it does not exist, or if either `foo.c' or `defs.h' is more recent
than it.

* How to update the file `foo.o': by running `cc' as stated. The
command does not explicitly mention `defs.h', but we presume that
`foo.c' includes it, and that that is why `defs.h' was added to
the prerequisites.

File: make.info, Node: Rule Syntax, Next: Prerequisite Types, Prev: Rule Example, Up: Rules

Rule Syntax
===========

In general, a rule looks like this:

TARGETS : PREREQUISITES
COMMAND
...

or like this:

TARGETS : PREREQUISITES ; COMMAND
COMMAND
...

The TARGETS are file names, separated by spaces. Wildcard
characters may be used (*note Using Wildcard Characters in File Names:
Wildcards.) and a name of the form `A(M)' represents member M in
archive file A (*note Archive Members as Targets: Archive Members.).
Usually there is only one target per rule, but occasionally there is a
reason to have more (*note Multiple Targets in a Rule: Multiple
Targets.).

The COMMAND lines start with a tab character. The first command may
appear on the line after the prerequisites, with a tab character, or may
appear on the same line, with a semicolon. Either way, the effect is
the same. *Note Writing the Commands in Rules: Commands.

Because dollar signs are used to start variable references, if you
really want a dollar sign in a rule you must write two of them, `$$'
(*note How to Use Variables: Using Variables.). You may split a long
line by inserting a backslash followed by a newline, but this is not
required, as `make' places no limit on the length of a line in a
makefile.

A rule tells `make' two things: when the targets are out of date,
and how to update them when necessary.

The criterion for being out of date is specified in terms of the
PREREQUISITES, which consist of file names separated by spaces.
(Wildcards and archive members (*note Archives::) are allowed here too.)
A target is out of date if it does not exist or if it is older than any
of the prerequisites (by comparison of last-modification times). The
idea is that the contents of the target file are computed based on
information in the prerequisites, so if any of the prerequisites
changes, the contents of the existing target file are no longer
necessarily valid.

How to update is specified by COMMANDS. These are lines to be
executed by the shell (normally `sh'), but with some extra features
(*note Writing the Commands in Rules: Commands.).

File: make.info, Node: Prerequisite Types, Next: Wildcards, Prev: Rule Syntax, Up: Rules

Types of Prerequisites
======================

There are actually two different types of prerequisites understood by
GNU `make': normal prerequisites such as described in the previous
section, and "order-only" prerequisites. A normal prerequisite
actually makes two statements: first, it imposes an order of execution
of build commands: any commands necessary to build any of a target's
prerequisites will be fully executed before any commands necessary to
build the target. Second, it imposes a dependency relationship: if any
prerequisite is newer than the target, then the target is considered
out-of-date and must be rebuilt.

Normally, this is exactly what you want: if a target's prerequisite
is updated, then the target should also be updated.

Occasionally, however, you have a situation where you want to impose
a specific ordering on the rules to be invoked _without_ forcing the
target to be updated if one of those rules is executed. In that case,
you want to define "order-only" prerequisites. Order-only
prerequisites can be specified by placing a pipe symbol (`|') in the
prerequisites list: any prerequisites to the left of the pipe symbol
are normal; any prerequisites to the right are order-only:

TARGETS : NORMAL-PREREQUISITES | ORDER-ONLY-PREREQUISITES

The normal prerequisites section may of course be empty. Also, you
may still declare multiple lines of prerequisites for the same target:
they are appended appropriately. Note that if you declare the same
file to be both a normal and an order-only prerequisite, the normal
prerequisite takes precedence (since they are a strict superset of the
behavior of an order-only prerequisite).

File: make.info, Node: Wildcards, Next: Directory Search, Prev: Prerequisite Types, Up: Rules

Using Wildcard Characters in File Names
=======================================

A single file name can specify many files using "wildcard
characters". The wildcard characters in `make' are `*', `?' and
`[...]', the same as in the Bourne shell. For example, `*.c' specifies
a list of all the files (in the working directory) whose names end in
`.c'.

The character `~' at the beginning of a file name also has special
significance. If alone, or followed by a slash, it represents your home
directory. For example `~/bin' expands to `/home/you/bin'. If the `~'
is followed by a word, the string represents the home directory of the
user named by that word. For example `~john/bin' expands to
`/home/john/bin'. On systems which don't have a home directory for
each user (such as MS-DOS or MS-Windows), this functionality can be
simulated by setting the environment variable HOME.

Wildcard expansion happens automatically in targets, in
prerequisites, and in commands (where the shell does the expansion).
In other contexts, wildcard expansion happens only if you request it
explicitly with the `wildcard' function.

The special significance of a wildcard character can be turned off by
preceding it with a backslash. Thus, `foo\*bar' would refer to a
specific file whose name consists of `foo', an asterisk, and `bar'.

* Menu:

* Wildcard Examples:: Several examples
* Wildcard Pitfall:: Problems to avoid.
* Wildcard Function:: How to cause wildcard expansion where
it does not normally take place.

File: make.info, Node: Wildcard Examples, Next: Wildcard Pitfall, Prev: Wildcards, Up: Wildcards

Wildcard Examples
-----------------

Wildcards can be used in the commands of a rule, where they are
expanded by the shell. For example, here is a rule to delete all the
object files:

clean:
rm -f *.o

Wildcards are also useful in the prerequisites of a rule. With the
following rule in the makefile, `make print' will print all the `.c'
files that have changed since the last time you printed them:

print: *.c
lpr -p $?
touch print

This rule uses `print' as an empty target file; see *Note Empty Target
Files to Record Events: Empty Targets. (The automatic variable `$?' is
used to print only those files that have changed; see *Note Automatic
Variables: Automatic.)

Wildcard expansion does not happen when you define a variable.
Thus, if you write this:

objects = *.o

then the value of the variable `objects' is the actual string `*.o'.
However, if you use the value of `objects' in a target, prerequisite or
command, wildcard expansion will take place at that time. To set
`objects' to the expansion, instead use:

objects := $(wildcard *.o)

*Note Wildcard Function::.

File: make.info, Node: Wildcard Pitfall, Next: Wildcard Function, Prev: Wildcard Examples, Up: Wildcards

Pitfalls of Using Wildcards
---------------------------

Now here is an example of a naive way of using wildcard expansion,
that does not do what you would intend. Suppose you would like to say
that the executable file `foo' is made from all the object files in the
directory, and you write this:

objects = *.o

foo : $(objects)
cc -o foo $(CFLAGS) $(objects)

The value of `objects' is the actual string `*.o'. Wildcard expansion
happens in the rule for `foo', so that each _existing_ `.o' file
becomes a prerequisite of `foo' and will be recompiled if necessary.

But what if you delete all the `.o' files? When a wildcard matches
no files, it is left as it is, so then `foo' will depend on the
oddly-named file `*.o'. Since no such file is likely to exist, `make'
will give you an error saying it cannot figure out how to make `*.o'.
This is not what you want!

Actually it is possible to obtain the desired result with wildcard
expansion, but you need more sophisticated techniques, including the
`wildcard' function and string substitution. *Note The Function
`wildcard': Wildcard Function.

Microsoft operating systems (MS-DOS and MS-Windows) use backslashes
to separate directories in pathnames, like so:

c:\foo\bar\baz.c

This is equivalent to the Unix-style `c:/foo/bar/baz.c' (the `c:'
part is the so-called drive letter). When `make' runs on these
systems, it supports backslashes as well as the Unix-style forward
slashes in pathnames. However, this support does _not_ include the
wildcard expansion, where backslash is a quote character. Therefore,
you _must_ use Unix-style slashes in these cases.

File: make.info, Node: Wildcard Function, Prev: Wildcard Pitfall, Up: Wildcards

The Function `wildcard'
-----------------------

Wildcard expansion happens automatically in rules. But wildcard
expansion does not normally take place when a variable is set, or
inside the arguments of a function. If you want to do wildcard
expansion in such places, you need to use the `wildcard' function, like
this:

$(wildcard PATTERN...)

This string, used anywhere in a makefile, is replaced by a
space-separated list of names of existing files that match one of the
given file name patterns. If no existing file name matches a pattern,
then that pattern is omitted from the output of the `wildcard'
function. Note that this is different from how unmatched wildcards
behave in rules, where they are used verbatim rather than ignored
(*note Wildcard Pitfall::).

One use of the `wildcard' function is to get a list of all the C
source files in a directory, like this:

$(wildcard *.c)

We can change the list of C source files into a list of object files
by replacing the `.c' suffix with `.o' in the result, like this:

$(patsubst %.c,%.o,$(wildcard *.c))

(Here we have used another function, `patsubst'. *Note Functions for
String Substitution and Analysis: Text Functions.)

Thus, a makefile to compile all C source files in the directory and
then link them together could be written as follows:

objects := $(patsubst %.c,%.o,$(wildcard *.c))

foo : $(objects)
cc -o foo $(objects)

(This takes advantage of the implicit rule for compiling C programs, so
there is no need to write explicit rules for compiling the files.
*Note The Two Flavors of Variables: Flavors, for an explanation of
`:=', which is a variant of `='.)

File: make.info, Node: Directory Search, Next: Phony Targets, Prev: Wildcards, Up: Rules

Searching Directories for Prerequisites
=======================================

For large systems, it is often desirable to put sources in a separate
directory from the binaries. The "directory search" features of `make'
facilitate this by searching several directories automatically to find
a prerequisite. When you redistribute the files among directories, you
do not need to change the individual rules, just the search paths.

* Menu:

File: make.info, Node: General Search, Next: Selective Search, Prev: Directory Search, Up: Directory Search

`VPATH': Search Path for All Prerequisites
------------------------------------------

The value of the `make' variable `VPATH' specifies a list of
directories that `make' should search. Most often, the directories are
expected to contain prerequisite files that are not in the current
directory; however, `VPATH' specifies a search list that `make' applies
for all files, including files which are targets of rules.

Thus, if a file that is listed as a target or prerequisite does not
exist in the current directory, `make' searches the directories listed
in `VPATH' for a file with that name. If a file is found in one of
them, that file may become the prerequisite (see below). Rules may then
specify the names of files in the prerequisite list as if they all
existed in the current directory. *Note Writing Shell Commands with
Directory Search: Commands/Search.

In the `VPATH' variable, directory names are separated by colons or
blanks. The order in which directories are listed is the order followed
by `make' in its search. (On MS-DOS and MS-Windows, semi-colons are
used as separators of directory names in `VPATH', since the colon can
be used in the pathname itself, after the drive letter.)

For example,

VPATH = src:../headers

specifies a path containing two directories, `src' and `../headers',
which `make' searches in that order.

With this value of `VPATH', the following rule,

foo.o : foo.c

is interpreted as if it were written like this:

foo.o : src/foo.c

assuming the file `foo.c' does not exist in the current directory but
is found in the directory `src'.

File: make.info, Node: Selective Search, Next: Search Algorithm, Prev: General Search, Up: Directory Search

The `vpath' Directive
---------------------

Similar to the `VPATH' variable, but more selective, is the `vpath'
directive (note lower case), which allows you to specify a search path
for a particular class of file names: those that match a particular
pattern. Thus you can supply certain search directories for one class
of file names and other directories (or none) for other file names.

There are three forms of the `vpath' directive:

`vpath PATTERN DIRECTORIES'
Specify the search path DIRECTORIES for file names that match
PATTERN.

The search path, DIRECTORIES, is a list of directories to be
searched, separated by colons (semi-colons on MS-DOS and
MS-Windows) or blanks, just like the search path used in the
`VPATH' variable.

`vpath PATTERN'
Clear out the search path associated with PATTERN.

`vpath'
Clear all search paths previously specified with `vpath'
directives.

A `vpath' pattern is a string containing a `%' character. The
string must match the file name of a prerequisite that is being searched
for, the `%' character matching any sequence of zero or more characters
(as in pattern rules; *note Defining and Redefining Pattern Rules:
Pattern Rules.). For example, `%.h' matches files that end in `.h'.
(If there is no `%', the pattern must match the prerequisite exactly,
which is not useful very often.)

`%' characters in a `vpath' directive's pattern can be quoted with
preceding backslashes (`\'). Backslashes that would otherwise quote
`%' characters can be quoted with more backslashes. Backslashes that
quote `%' characters or other backslashes are removed from the pattern
before it is compared to file names. Backslashes that are not in
danger of quoting `%' characters go unmolested.

When a prerequisite fails to exist in the current directory, if the
PATTERN in a `vpath' directive matches the name of the prerequisite
file, then the DIRECTORIES in that directive are searched just like
(and before) the directories in the `VPATH' variable.

For example,

vpath %.h ../headers

tells `make' to look for any prerequisite whose name ends in `.h' in
the directory `../headers' if the file is not found in the current
directory.

If several `vpath' patterns match the prerequisite file's name, then
`make' processes each matching `vpath' directive one by one, searching
all the directories mentioned in each directive. `make' handles
multiple `vpath' directives in the order in which they appear in the
makefile; multiple directives with the same pattern are independent of
each other.

Thus,

vpath %.c foo
vpath % blish
vpath %.c bar

will look for a file ending in `.c' in `foo', then `blish', then `bar',
while

vpath %.c foo:bar
vpath % blish

will look for a file ending in `.c' in `foo', then `bar', then `blish'.

File: make.info, Node: Search Algorithm, Next: Commands/Search, Prev: Selective Search, Up: Directory Search

How Directory Searches are Performed
------------------------------------

When a prerequisite is found through directory search, regardless of
type (general or selective), the pathname located may not be the one
that `make' actually provides you in the prerequisite list. Sometimes
the path discovered through directory search is thrown away.

The algorithm `make' uses to decide whether to keep or abandon a
path found via directory search is as follows:

1. If a target file does not exist at the path specified in the
makefile, directory search is performed.

2. If the directory search is successful, that path is kept and this
file is tentatively stored as the target.

3. All prerequisites of this target are examined using this same
method.

4. After processing the prerequisites, the target may or may not need
to be rebuilt:

a. If the target does _not_ need to be rebuilt, the path to the
file found during directory search is used for any
prerequisite lists which contain this target. In short, if
`make' doesn't need to rebuild the target then you use the
path found via directory search.

b. If the target _does_ need to be rebuilt (is out-of-date), the
pathname found during directory search is _thrown away_, and
the target is rebuilt using the file name specified in the
makefile. In short, if `make' must rebuild, then the target
is rebuilt locally, not in the directory found via directory
search.

This algorithm may seem complex, but in practice it is quite often
exactly what you want.

Other versions of `make' use a simpler algorithm: if the file does
not exist, and it is found via directory search, then that pathname is
always used whether or not the target needs to be built. Thus, if the
target is rebuilt it is created at the pathname discovered during
directory search.

If, in fact, this is the behavior you want for some or all of your
directories, you can use the `GPATH' variable to indicate this to
`make'.

`GPATH' has the same syntax and format as `VPATH' (that is, a space-
or colon-delimited list of pathnames). If an out-of-date target is
found by directory search in a directory that also appears in `GPATH',
then that pathname is not thrown away. The target is rebuilt using the
expanded path.

File: make.info, Node: Commands/Search, Next: Implicit/Search, Prev: Search Algorithm, Up: Directory Search

Writing Shell Commands with Directory Search
--------------------------------------------

When a prerequisite is found in another directory through directory
search, this cannot change the commands of the rule; they will execute
as written. Therefore, you must write the commands with care so that
they will look for the prerequisite in the directory where `make' finds
it.

This is done with the "automatic variables" such as `$^' (*note
Automatic Variables: Automatic.). For instance, the value of `$^' is a
list of all the prerequisites of the rule, including the names of the
directories in which they were found, and the value of `$@' is the
target. Thus:

foo.o : foo.c
cc -c $(CFLAGS) $^ -o $@

(The variable `CFLAGS' exists so you can specify flags for C
compilation by implicit rules; we use it here for consistency so it will
affect all C compilations uniformly; *note Variables Used by Implicit
Rules: Implicit Variables..)

Often the prerequisites include header files as well, which you do
not want to mention in the commands. The automatic variable `$<' is
just the first prerequisite:

VPATH = src:../headers
foo.o : foo.c defs.h hack.h
cc -c $(CFLAGS) $< -o $@

File: make.info, Node: Implicit/Search, Next: Libraries/Search, Prev: Commands/Search, Up: Directory Search

Directory Search and Implicit Rules
-----------------------------------

The search through the directories specified in `VPATH' or with
`vpath' also happens during consideration of implicit rules (*note
Using Implicit Rules: Implicit Rules.).

For example, when a file `foo.o' has no explicit rule, `make'
considers implicit rules, such as the built-in rule to compile `foo.c'
if that file exists. If such a file is lacking in the current
directory, the appropriate directories are searched for it. If `foo.c'
exists (or is mentioned in the makefile) in any of the directories, the
implicit rule for C compilation is applied.

The commands of implicit rules normally use automatic variables as a
matter of necessity; consequently they will use the file names found by
directory search with no extra effort.

File: make.info, Node: Libraries/Search, Prev: Implicit/Search, Up: Directory Search

Directory Search for Link Libraries
-----------------------------------

Directory search applies in a special way to libraries used with the
linker. This special feature comes into play when you write a
prerequisite whose name is of the form `-lNAME'. (You can tell
something strange is going on here because the prerequisite is normally
the name of a file, and the _file name_ of a library generally looks
like `libNAME.a', not like `-lNAME'.)

When a prerequisite's name has the form `-lNAME', `make' handles it
specially by searching for the file `libNAME.so' in the current
directory, in directories specified by matching `vpath' search paths
and the `VPATH' search path, and then in the directories `/lib',
`/usr/lib', and `PREFIX/lib' (normally `/usr/local/lib', but
MS-DOS/MS-Windows versions of `make' behave as if PREFIX is defined to
be the root of the DJGPP installation tree).

If that file is not found, then the file `libNAME.a' is searched
for, in the same directories as above.

For example, if there is a `/usr/lib/libcurses.a' library on your
system (and no `/usr/lib/libcurses.so' file), then

foo : foo.c -lcurses
cc $^ -o $@

would cause the command `cc foo.c /usr/lib/libcurses.a -o foo' to be
executed when `foo' is older than `foo.c' or than
`/usr/lib/libcurses.a'.

Although the default set of files to be searched for is `libNAME.so'
and `libNAME.a', this is customizable via the `.LIBPATTERNS' variable.
Each word in the value of this variable is a pattern string. When a
prerequisite like `-lNAME' is seen, `make' will replace the percent in
each pattern in the list with NAME and perform the above directory
searches using that library filename. If no library is found, the next
word in the list will be used.

The default value for `.LIBPATTERNS' is "`lib%.so lib%.a'", which
provides the default behavior described above.

You can turn off link library expansion completely by setting this
variable to an empty value.

File: make.info, Node: Phony Targets, Next: Force Targets, Prev: Directory Search, Up: Rules

Phony Targets
=============

A phony target is one that is not really the name of a file. It is
just a name for some commands to be executed when you make an explicit
request. There are two reasons to use a phony target: to avoid a
conflict with a file of the same name, and to improve performance.

If you write a rule whose commands will not create the target file,
the commands will be executed every time the target comes up for
remaking. Here is an example:

clean:
rm *.o temp

Because the `rm' command does not create a file named `clean', probably
no such file will ever exist. Therefore, the `rm' command will be
executed every time you say `make clean'.

The phony target will cease to work if anything ever does create a
file named `clean' in this directory. Since it has no prerequisites,
the file `clean' would inevitably be considered up to date, and its
commands would not be executed. To avoid this problem, you can
explicitly declare the target to be phony, using the special target
`.PHONY' (*note Special Built-in Target Names: Special Targets.) as
follows:

.PHONY : clean

Once this is done, `make clean' will run the commands regardless of
whether there is a file named `clean'.

Since it knows that phony targets do not name actual files that
could be remade from other files, `make' skips the implicit rule search
for phony targets (*note Implicit Rules::). This is why declaring a
target phony is good for performance, even if you are not worried about
the actual file existing.

Thus, you first write the line that states that `clean' is a phony
target, then you write the rule, like this:

.PHONY: clean
clean:
rm *.o temp

Another example of the usefulness of phony targets is in conjunction
with recursive invocations of `make' (for more information, see *Note
Recursive Use of `make': Recursion). In this case the makefile will
often contain a variable which lists a number of subdirectories to be
built. One way to handle this is with one rule whose command is a
shell loop over the subdirectories, like this:

SUBDIRS = foo bar baz

subdirs:
for dir in $(SUBDIRS); do \
$(MAKE) -C $$dir; \
done

There are a few problems with this method, however. First, any error
detected in a submake is not noted by this rule, so it will continue to
build the rest of the directories even when one fails. This can be
overcome by adding shell commands to note the error and exit, but then
it will do so even if `make' is invoked with the `-k' option, which is
unfortunate. Second, and perhaps more importantly, you cannot take
advantage of the parallel build capabilities of make using this method,
since there is only one rule.

By declaring the subdirectories as phony targets (you must do this as
the subdirectory obviously always exists; otherwise it won't be built)
you can remove these problems:

SUBDIRS = foo bar baz

.PHONY: subdirs $(SUBDIRS)

subdirs: $(SUBDIRS)

$(SUBDIRS):
$(MAKE) -C $@

foo: baz

Here we've also declared that the `foo' subdirectory cannot be built
until after the `baz' subdirectory is complete; this kind of
relationship declaration is particularly important when attempting
parallel builds.

A phony target should not be a prerequisite of a real target file;
if it is, its commands are run every time `make' goes to update that
file. As long as a phony target is never a prerequisite of a real
target, the phony target commands will be executed only when the phony
target is a specified goal (*note Arguments to Specify the Goals:
Goals.).

Phony targets can have prerequisites. When one directory contains
multiple programs, it is most convenient to describe all of the
programs in one makefile `./Makefile'. Since the target remade by
default will be the first one in the makefile, it is common to make
this a phony target named `all' and give it, as prerequisites, all the
individual programs. For example:

all : prog1 prog2 prog3
.PHONY : all

prog1 : prog1.o utils.o
cc -o prog1 prog1.o utils.o

prog2 : prog2.o
cc -o prog2 prog2.o

prog3 : prog3.o sort.o utils.o
cc -o prog3 prog3.o sort.o utils.o

Now you can say just `make' to remake all three programs, or specify as
arguments the ones to remake (as in `make prog1 prog3').

When one phony target is a prerequisite of another, it serves as a
subroutine of the other. For example, here `make cleanall' will delete
the object files, the difference files, and the file `program':

.PHONY: cleanall cleanobj cleandiff

cleanall : cleanobj cleandiff
rm program

cleanobj :
rm *.o

cleandiff :
rm *.diff

File: make.info, Node: Force Targets, Next: Empty Targets, Prev: Phony Targets, Up: Rules

Rules without Commands or Prerequisites
=======================================

If a rule has no prerequisites or commands, and the target of the
rule is a nonexistent file, then `make' imagines this target to have
been updated whenever its rule is run. This implies that all targets
depending on this one will always have their commands run.

An example will illustrate this:

clean: FORCE
rm $(objects)
FORCE:

Here the target `FORCE' satisfies the special conditions, so the
target `clean' that depends on it is forced to run its commands. There
is nothing special about the name `FORCE', but that is one name
commonly used this way.

As you can see, using `FORCE' this way has the same results as using
`.PHONY: clean'.

Using `.PHONY' is more explicit and more efficient. However, other
versions of `make' do not support `.PHONY'; thus `FORCE' appears in
many makefiles. *Note Phony Targets::.

File: make.info, Node: Empty Targets, Next: Special Targets, Prev: Force Targets, Up: Rules

Empty Target Files to Record Events
===================================

The "empty target" is a variant of the phony target; it is used to
hold commands for an action that you request explicitly from time to
time. Unlike a phony target, this target file can really exist; but
the file's contents do not matter, and usually are empty.

The purpose of the empty target file is to record, with its
last-modification time, when the rule's commands were last executed. It
does so because one of the commands is a `touch' command to update the
target file.

The empty target file should have some prerequisites (otherwise it
doesn't make sense). When you ask to remake the empty target, the
commands are executed if any prerequisite is more recent than the
target; in other words, if a prerequisite has changed since the last
time you remade the target. Here is an example:

print: foo.c bar.c
lpr -p $?
touch print

With this rule, `make print' will execute the `lpr' command if either
source file has changed since the last `make print'. The automatic
variable `$?' is used to print only those files that have changed
(*note Automatic Variables: Automatic.).

File: make.info, Node: Special Targets, Next: Multiple Targets, Prev: Empty Targets, Up: Rules

Special Built-in Target Names
=============================

Certain names have special meanings if they appear as targets.

`.PHONY'
The prerequisites of the special target `.PHONY' are considered to
be phony targets. When it is time to consider such a target,
`make' will run its commands unconditionally, regardless of
whether a file with that name exists or what its last-modification
time is. *Note Phony Targets: Phony Targets.

`.SUFFIXES'
The prerequisites of the special target `.SUFFIXES' are the list
of suffixes to be used in checking for suffix rules. *Note
Old-Fashioned Suffix Rules: Suffix Rules.

`.DEFAULT'
The commands specified for `.DEFAULT' are used for any target for
which no rules are found (either explicit rules or implicit rules).
*Note Last Resort::. If `.DEFAULT' commands are specified, every
file mentioned as a prerequisite, but not as a target in a rule,
will have these commands executed on its behalf. *Note Implicit
Rule Search Algorithm: Implicit Rule Search.

`.PRECIOUS'
The targets which `.PRECIOUS' depends on are given the following
special treatment: if `make' is killed or interrupted during the
execution of their commands, the target is not deleted. *Note
Interrupting or Killing `make': Interrupts. Also, if the target
is an intermediate file, it will not be deleted after it is no
longer needed, as is normally done. *Note Chains of Implicit
Rules: Chained Rules. In this latter respect it overlaps with the
`.SECONDARY' special target.

You can also list the target pattern of an implicit rule (such as
`%.o') as a prerequisite file of the special target `.PRECIOUS' to
preserve intermediate files created by rules whose target patterns
match that file's name.

`.INTERMEDIATE'
The targets which `.INTERMEDIATE' depends on are treated as
intermediate files. *Note Chains of Implicit Rules: Chained Rules.
`.INTERMEDIATE' with no prerequisites has no effect.

`.SECONDARY'
The targets which `.SECONDARY' depends on are treated as
intermediate files, except that they are never automatically
deleted. *Note Chains of Implicit Rules: Chained Rules.

`.SECONDARY' with no prerequisites causes all targets to be treated
as secondary (i.e., no target is removed because it is considered
intermediate).

`.DELETE_ON_ERROR'
If `.DELETE_ON_ERROR' is mentioned as a target anywhere in the
makefile, then `make' will delete the target of a rule if it has
changed and its commands exit with a nonzero exit status, just as
it does when it receives a signal. *Note Errors in Commands:
Errors.

`.IGNORE'
If you specify prerequisites for `.IGNORE', then `make' will
ignore errors in execution of the commands run for those particular
files. The commands for `.IGNORE' are not meaningful.

If mentioned as a target with no prerequisites, `.IGNORE' says to
ignore errors in execution of commands for all files. This usage
of `.IGNORE' is supported only for historical compatibility. Since
this affects every command in the makefile, it is not very useful;
we recommend you use the more selective ways to ignore errors in
specific commands. *Note Errors in Commands: Errors.

`.LOW_RESOLUTION_TIME'
If you specify prerequisites for `.LOW_RESOLUTION_TIME', `make'
assumes that these files are created by commands that generate low
resolution time stamps. The commands for `.LOW_RESOLUTION_TIME'
are not meaningful.

The high resolution file time stamps of many modern hosts lessen
the chance of `make' incorrectly concluding that a file is up to
date. Unfortunately, these hosts provide no way to set a high
resolution file time stamp, so commands like `cp -p' that
explicitly set a file's time stamp must discard its subsecond
part. If a file is created by such a command, you should list it
as a prerequisite of `.LOW_RESOLUTION_TIME' so that `make' does
not mistakenly conclude that the file is out of date. For example:

.LOW_RESOLUTION_TIME: dst
dst: src
cp -p src dst

Since `cp -p' discards the subsecond part of `src''s time stamp,
`dst' is typically slightly older than `src' even when it is up to
date. The `.LOW_RESOLUTION_TIME' line causes `make' to consider
`dst' to be up to date if its time stamp is at the start of the
same second that `src''s time stamp is in.

Due to a limitation of the archive format, archive member time
stamps are always low resolution. You need not list archive
members as prerequisites of `.LOW_RESOLUTION_TIME', as `make' does
this automatically.

`.SILENT'
If you specify prerequisites for `.SILENT', then `make' will not
print the commands to remake those particular files before
executing them. The commands for `.SILENT' are not meaningful.

If mentioned as a target with no prerequisites, `.SILENT' says not
to print any commands before executing them. This usage of
`.SILENT' is supported only for historical compatibility. We
recommend you use the more selective ways to silence specific
commands. *Note Command Echoing: Echoing. If you want to silence
all commands for a particular run of `make', use the `-s' or
`--silent' option (*note Options Summary::).

`.EXPORT_ALL_VARIABLES'
Simply by being mentioned as a target, this tells `make' to export
all variables to child processes by default. *Note Communicating
Variables to a Sub-`make': Variables/Recursion.

`.NOTPARALLEL'
If `.NOTPARALLEL' is mentioned as a target, then this invocation of
`make' will be run serially, even if the `-j' option is given.
Any recursively invoked `make' command will still be run in
parallel (unless its makefile contains this target). Any
prerequisites on this target are ignored.

Any defined implicit rule suffix also counts as a special target if
it appears as a target, and so does the concatenation of two suffixes,
such as `.c.o'. These targets are suffix rules, an obsolete way of
defining implicit rules (but a way still widely used). In principle,
any target name could be special in this way if you break it in two and
add both pieces to the suffix list. In practice, suffixes normally
begin with `.', so these special target names also begin with `.'.
*Note Old-Fashioned Suffix Rules: Suffix Rules.

File: make.info, Node: Multiple Targets, Next: Multiple Rules, Prev: Special Targets, Up: Rules

Multiple Targets in a Rule
==========================

A rule with multiple targets is equivalent to writing many rules,
each with one target, and all identical aside from that. The same
commands apply to all the targets, but their effects may vary because
you can substitute the actual target name into the command using `$@'.
The rule contributes the same prerequisites to all the targets also.

This is useful in two cases.

* You want just prerequisites, no commands. For example:

kbd.o command.o files.o: command.h

gives an additional prerequisite to each of the three object files
mentioned.

* Similar commands work for all the targets. The commands do not
need to be absolutely identical, since the automatic variable `$@'
can be used to substitute the particular target to be remade into
the commands (*note Automatic Variables: Automatic.). For example:

bigoutput littleoutput : text.g
generate text.g -$(subst output,,$@) > $@

is equivalent to

bigoutput : text.g
generate text.g -big > bigoutput
littleoutput : text.g
generate text.g -little > littleoutput

Here we assume the hypothetical program `generate' makes two types
of output, one if given `-big' and one if given `-little'. *Note
Functions for String Substitution and Analysis: Text Functions,
for an explanation of the `subst' function.

Suppose you would like to vary the prerequisites according to the
target, much as the variable `$@' allows you to vary the commands. You
cannot do this with multiple targets in an ordinary rule, but you can
do it with a "static pattern rule". *Note Static Pattern Rules: Static
Pattern.

File: make.info, Node: Multiple Rules, Next: Static Pattern, Prev: Multiple Targets, Up: Rules

Multiple Rules for One Target
=============================

One file can be the target of several rules. All the prerequisites
mentioned in all the rules are merged into one list of prerequisites for
the target. If the target is older than any prerequisite from any rule,
the commands are executed.

There can only be one set of commands to be executed for a file. If
more than one rule gives commands for the same file, `make' uses the
last set given and prints an error message. (As a special case, if the
file's name begins with a dot, no error message is printed. This odd
behavior is only for compatibility with other implementations of
`make'... you should avoid using it). Occasionally it is useful to
have the same target invoke multiple commands which are defined in
different parts of your makefile; you can use "double-colon rules"
(*note Double-Colon::) for this.

An extra rule with just prerequisites can be used to give a few extra
prerequisites to many files at once. For example, makefiles often have
a variable, such as `objects', containing a list of all the compiler
output files in the system being made. An easy way to say that all of
them must be recompiled if `config.h' changes is to write the following:

objects = foo.o bar.o
foo.o : defs.h
bar.o : defs.h test.h
$(objects) : config.h

This could be inserted or taken out without changing the rules that
really specify how to make the object files, making it a convenient
form to use if you wish to add the additional prerequisite
intermittently.

Another wrinkle is that the additional prerequisites could be
specified with a variable that you set with a command argument to `make'
(*note Overriding Variables: Overriding.). For example,

extradeps=
$(objects) : $(extradeps)

means that the command `make extradeps=foo.h' will consider `foo.h' as
a prerequisite of each object file, but plain `make' will not.

If none of the explicit rules for a target has commands, then `make'
searches for an applicable implicit rule to find some commands *note
Using Implicit Rules: Implicit Rules.).

File: make.info, Node: Static Pattern, Next: Double-Colon, Prev: Multiple Rules, Up: Rules

Static Pattern Rules
====================

"Static pattern rules" are rules which specify multiple targets and
construct the prerequisite names for each target based on the target
name. They are more general than ordinary rules with multiple targets
because the targets do not have to have identical prerequisites. Their
prerequisites must be _analogous_, but not necessarily _identical_.

* Menu:

* Static Usage:: The syntax of static pattern rules.
* Static versus Implicit:: When are they better than implicit rules?

File: make.info, Node: Static Usage, Next: Static versus Implicit, Prev: Static Pattern, Up: Static Pattern

Syntax of Static Pattern Rules
------------------------------

Here is the syntax of a static pattern rule:

TARGETS ...: TARGET-PATTERN: PREREQ-PATTERNS ...
COMMANDS
...

The TARGETS list specifies the targets that the rule applies to. The
targets can contain wildcard characters, just like the targets of
ordinary rules (*note Using Wildcard Characters in File Names:
Wildcards.).

The TARGET-PATTERN and PREREQ-PATTERNS say how to compute the
prerequisites of each target. Each target is matched against the
TARGET-PATTERN to extract a part of the target name, called the "stem".
This stem is substituted into each of the PREREQ-PATTERNS to make the
prerequisite names (one from each PREREQ-PATTERN).

Each pattern normally contains the character `%' just once. When the
TARGET-PATTERN matches a target, the `%' can match any part of the
target name; this part is called the "stem". The rest of the pattern
must match exactly. For example, the target `foo.o' matches the
pattern `%.o', with `foo' as the stem. The targets `foo.c' and
`foo.out' do not match that pattern.

The prerequisite names for each target are made by substituting the
stem for the `%' in each prerequisite pattern. For example, if one
prerequisite pattern is `%.c', then substitution of the stem `foo'
gives the prerequisite name `foo.c'. It is legitimate to write a
prerequisite pattern that does not contain `%'; then this prerequisite
is the same for all targets.

`%' characters in pattern rules can be quoted with preceding
backslashes (`\'). Backslashes that would otherwise quote `%'
characters can be quoted with more backslashes. Backslashes that quote
`%' characters or other backslashes are removed from the pattern before
it is compared to file names or has a stem substituted into it.
Backslashes that are not in danger of quoting `%' characters go
unmolested. For example, the pattern `the\%weird\\%pattern\\' has
`the%weird\' preceding the operative `%' character, and `pattern\\'
following it. The final two backslashes are left alone because they
cannot affect any `%' character.

Here is an example, which compiles each of `foo.o' and `bar.o' from
the corresponding `.c' file:

objects = foo.o bar.o

all: $(objects)

$(objects): %.o: %.c
$(CC) -c $(CFLAGS) $< -o $@

Here `$<' is the automatic variable that holds the name of the
prerequisite and `$@' is the automatic variable that holds the name of
the target; see *Note Automatic Variables: Automatic.

Each target specified must match the target pattern; a warning is
issued for each target that does not. If you have a list of files,
only some of which will match the pattern, you can use the `filter'
function to remove nonmatching file names (*note Functions for String
Substitution and Analysis: Text Functions.):

files = foo.elc bar.o lose.o

$(filter %.o,$(files)): %.o: %.c
$(CC) -c $(CFLAGS) $< -o $@
$(filter %.elc,$(files)): %.elc: %.el
emacs -f batch-byte-compile $<

In this example the result of `$(filter %.o,$(files))' is `bar.o
lose.o', and the first static pattern rule causes each of these object
files to be updated by compiling the corresponding C source file. The
result of `$(filter %.elc,$(files))' is `foo.elc', so that file is made
from `foo.el'.

Another example shows how to use `$*' in static pattern rules:

bigoutput littleoutput : %output : text.g
generate text.g -$* > $@

When the `generate' command is run, `$*' will expand to the stem,
either `big' or `little'.

File: make.info, Node: Static versus Implicit, Prev: Static Usage, Up: Static Pattern

Static Pattern Rules versus Implicit Rules
------------------------------------------

A static pattern rule has much in common with an implicit rule
defined as a pattern rule (*note Defining and Redefining Pattern Rules:
Pattern Rules.). Both have a pattern for the target and patterns for
constructing the names of prerequisites. The difference is in how
`make' decides _when_ the rule applies.

An implicit rule _can_ apply to any target that matches its pattern,
but it _does_ apply only when the target has no commands otherwise
specified, and only when the prerequisites can be found. If more than
one implicit rule appears applicable, only one applies; the choice
depends on the order of rules.

By contrast, a static pattern rule applies to the precise list of
targets that you specify in the rule. It cannot apply to any other
target and it invariably does apply to each of the targets specified.
If two conflicting rules apply, and both have commands, that's an error.

The static pattern rule can be better than an implicit rule for these
reasons:

* You may wish to override the usual implicit rule for a few files
whose names cannot be categorized syntactically but can be given
in an explicit list.

* If you cannot be sure of the precise contents of the directories
you are using, you may not be sure which other irrelevant files
might lead `make' to use the wrong implicit rule. The choice
might depend on the order in which the implicit rule search is
done. With static pattern rules, there is no uncertainty: each
rule applies to precisely the targets specified.

File: make.info, Node: Double-Colon, Next: Automatic Prerequisites, Prev: Static Pattern, Up: Rules

Double-Colon Rules
==================

"Double-colon" rules are rules written with `::' instead of `:'
after the target names. They are handled differently from ordinary
rules when the same target appears in more than one rule.

When a target appears in multiple rules, all the rules must be the
same type: all ordinary, or all double-colon. If they are
double-colon, each of them is independent of the others. Each
double-colon rule's commands are executed if the target is older than
any prerequisites of that rule. If there are no prerequisites for that
rule, its commands are always executed (even if the target already
exists). This can result in executing none, any, or all of the
double-colon rules.

Double-colon rules with the same target are in fact completely
separate from one another. Each double-colon rule is processed
individually, just as rules with different targets are processed.

The double-colon rules for a target are executed in the order they
appear in the makefile. However, the cases where double-colon rules
really make sense are those where the order of executing the commands
would not matter.

Double-colon rules are somewhat obscure and not often very useful;
they provide a mechanism for cases in which the method used to update a
target differs depending on which prerequisite files caused the update,
and such cases are rare.

Each double-colon rule should specify commands; if it does not, an
implicit rule will be used if one applies. *Note Using Implicit Rules:
Implicit Rules.

File: make.info, Node: Automatic Prerequisites, Prev: Double-Colon, Up: Rules

Generating Prerequisites Automatically
======================================

In the makefile for a program, many of the rules you need to write
often say only that some object file depends on some header file. For
example, if `main.c' uses `defs.h' via an `#include', you would write:

main.o: defs.h

You need this rule so that `make' knows that it must remake `main.o'
whenever `defs.h' changes. You can see that for a large program you
would have to write dozens of such rules in your makefile. And, you
must always be very careful to update the makefile every time you add
or remove an `#include'.

To avoid this hassle, most modern C compilers can write these rules
for you, by looking at the `#include' lines in the source files.
Usually this is done with the `-M' option to the compiler. For
example, the command:

cc -M main.c

generates the output:

main.o : main.c defs.h

Thus you no longer have to write all those rules yourself. The
compiler will do it for you.

Note that such a prerequisite constitutes mentioning `main.o' in a
makefile, so it can never be considered an intermediate file by implicit
rule search. This means that `make' won't ever remove the file after
using it; *note Chains of Implicit Rules: Chained Rules..

With old `make' programs, it was traditional practice to use this
compiler feature to generate prerequisites on demand with a command like
`make depend'. That command would create a file `depend' containing
all the automatically-generated prerequisites; then the makefile could
use `include' to read them in (*note Include::).

In GNU `make', the feature of remaking makefiles makes this practice
obsolete--you need never tell `make' explicitly to regenerate the
prerequisites, because it always regenerates any makefile that is out
of date. *Note Remaking Makefiles::.

The practice we recommend for automatic prerequisite generation is
to have one makefile corresponding to each source file. For each
source file `NAME.c' there is a makefile `NAME.d' which lists what
files the object file `NAME.o' depends on. That way only the source
files that have changed need to be rescanned to produce the new
prerequisites.

Here is the pattern rule to generate a file of prerequisites (i.e.,
a makefile) called `NAME.d' from a C source file called `NAME.c':

%.d: %.c

$(CC) -M $(CPPFLAGS) $< > $@.$$$$; \
sed 's,$$*$\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
rm -f $@.$$$$

*Note Pattern Rules::, for information on defining pattern rules. The
`-e' flag to the shell causes it to exit immediately if the `$(CC)'
command (or any other command) fails (exits with a nonzero status).

With the GNU C compiler, you may wish to use the `-MM' flag instead
of `-M'. This omits prerequisites on system header files. *Note
Options Controlling the Preprocessor: (gcc.info)Preprocessor Options,
for details.

The purpose of the `sed' command is to translate (for example):

main.o : main.c defs.h

into:

main.o main.d : main.c defs.h

This makes each `.d' file depend on all the source and header files
that the corresponding `.o' file depends on. `make' then knows it must
regenerate the prerequisites whenever any of the source or header files
changes.

Once you've defined the rule to remake the `.d' files, you then use
the `include' directive to read them all in. *Note Include::. For
example:

sources = foo.c bar.c

include $(sources:.c=.d)

(This example uses a substitution variable reference to translate the
list of source files `foo.c bar.c' into a list of prerequisite
makefiles, `foo.d bar.d'. *Note Substitution Refs::, for full
information on substitution references.) Since the `.d' files are
makefiles like any others, `make' will remake them as necessary with no
further work from you. *Note Remaking Makefiles::.

Note that the `.d' files contain target definitions; you should be
sure to place the `include' directive _after_ the first, default target
in your makefiles or run the risk of having a random object file become
the default target. *Note How Make Works::.

File: make.info, Node: Commands, Next: Using Variables, Prev: Rules, Up: Top

Writing the Commands in Rules
*****************************

The commands of a rule consist of shell command lines to be executed
one by one. Each command line must start with a tab, except that the
first command line may be attached to the target-and-prerequisites line
with a semicolon in between. Blank lines and lines of just comments
may appear among the command lines; they are ignored. (But beware, an
apparently "blank" line that begins with a tab is _not_ blank! It is an
empty command; *note Empty Commands::.)

Users use many different shell programs, but commands in makefiles
are always interpreted by `/bin/sh' unless the makefile specifies
otherwise. *Note Command Execution: Execution.

The shell that is in use determines whether comments can be written
on command lines, and what syntax they use. When the shell is
`/bin/sh', a `#' starts a comment that extends to the end of the line.
The `#' does not have to be at the beginning of a line. Text on a line
before a `#' is not part of the comment.

* Menu:

File: make.info, Node: Echoing, Next: Execution, Prev: Commands, Up: Commands

Command Echoing
===============

Normally `make' prints each command line before it is executed. We
call this "echoing" because it gives the appearance that you are typing
the commands yourself.

When a line starts with `@', the echoing of that line is suppressed.
The `@' is discarded before the command is passed to the shell.
Typically you would use this for a command whose only effect is to print
something, such as an `echo' command to indicate progress through the
makefile:

@echo About to make distribution files

When `make' is given the flag `-n' or `--just-print' it only echoes
commands, it won't execute them. *Note Summary of Options: Options
Summary. In this case and only this case, even the commands starting
with `@' are printed. This flag is useful for finding out which
commands `make' thinks are necessary without actually doing them.

The `-s' or `--silent' flag to `make' prevents all echoing, as if
all commands started with `@'. A rule in the makefile for the special
target `.SILENT' without prerequisites has the same effect (*note
Special Built-in Target Names: Special Targets.). `.SILENT' is
essentially obsolete since `@' is more flexible.

File: make.info, Node: Execution, Next: Parallel, Prev: Echoing, Up: Commands

Command Execution
=================

When it is time to execute commands to update a target, they are
executed by making a new subshell for each line. (In practice, `make'
may take shortcuts that do not affect the results.)

*Please note:* this implies that shell commands such as `cd' that
set variables local to each process will not affect the following
command lines. (1) If you want to use `cd' to affect the next command,
put the two on a single line with a semicolon between them. Then
`make' will consider them a single command and pass them, together, to
a shell which will execute them in sequence. For example:

foo : bar/lose
cd bar; gobble lose > ../foo

If you would like to split a single shell command into multiple
lines of text, you must use a backslash at the end of all but the last
subline. Such a sequence of lines is combined into a single line, by
deleting the backslash-newline sequences, before passing it to the
shell. Thus, the following is equivalent to the preceding example:

foo : bar/lose
cd bar; \
gobble lose > ../foo

The program used as the shell is taken from the variable `SHELL'.
By default, the program `/bin/sh' is used.

On MS-DOS, if `SHELL' is not set, the value of the variable
`COMSPEC' (which is always set) is used instead.

The processing of lines that set the variable `SHELL' in Makefiles
is different on MS-DOS. The stock shell, `command.com', is
ridiculously limited in its functionality and many users of `make' tend
to install a replacement shell. Therefore, on MS-DOS, `make' examines
the value of `SHELL', and changes its behavior based on whether it
points to a Unix-style or DOS-style shell. This allows reasonable
functionality even if `SHELL' points to `command.com'.

If `SHELL' points to a Unix-style shell, `make' on MS-DOS
additionally checks whether that shell can indeed be found; if not, it
ignores the line that sets `SHELL'. In MS-DOS, GNU `make' searches for
the shell in the following places:

1. In the precise place pointed to by the value of `SHELL'. For
example, if the makefile specifies `SHELL = /bin/sh', `make' will
look in the directory `/bin' on the current drive.

2. In the current directory.

3. In each of the directories in the `PATH' variable, in order.

In every directory it examines, `make' will first look for the
specific file (`sh' in the example above). If this is not found, it
will also look in that directory for that file with one of the known
extensions which identify executable files. For example `.exe',
`.com', `.bat', `.btm', `.sh', and some others.

If any of these attempts is successful, the value of `SHELL' will be
set to the full pathname of the shell as found. However, if none of
these is found, the value of `SHELL' will not be changed, and thus the
line that sets it will be effectively ignored. This is so `make' will
only support features specific to a Unix-style shell if such a shell is
actually installed on the system where `make' runs.

Note that this extended search for the shell is limited to the cases
where `SHELL' is set from the Makefile; if it is set in the environment
or command line, you are expected to set it to the full pathname of the
shell, exactly as things are on Unix.

The effect of the above DOS-specific processing is that a Makefile
that says `SHELL = /bin/sh' (as many Unix makefiles do), will work on
MS-DOS unaltered if you have e.g. `sh.exe' installed in some directory
along your `PATH'.

Unlike most variables, the variable `SHELL' is never set from the
environment. This is because the `SHELL' environment variable is used
to specify your personal choice of shell program for interactive use.
It would be very bad for personal choices like this to affect the
functioning of makefiles. *Note Variables from the Environment:
Environment. However, on MS-DOS and MS-Windows the value of `SHELL' in
the environment *is* used, since on those systems most users do not set
this variable, and therefore it is most likely set specifically to be
used by `make'. On MS-DOS, if the setting of `SHELL' is not suitable
for `make', you can set the variable `MAKESHELL' to the shell that
`make' should use; this will override the value of `SHELL'.

---------- Footnotes ----------

(1) On MS-DOS, the value of current working directory is *global*,
so changing it _will_ affect the following command lines on those
systems.

File: make.info, Node: Parallel, Next: Errors, Prev: Execution, Up: Commands

Parallel Execution
==================

GNU `make' knows how to execute several commands at once. Normally,
`make' will execute only one command at a time, waiting for it to
finish before executing the next. However, the `-j' or `--jobs' option
tells `make' to execute many commands simultaneously.

On MS-DOS, the `-j' option has no effect, since that system doesn't
support multi-processing.

If the `-j' option is followed by an integer, this is the number of
commands to execute at once; this is called the number of "job slots".
If there is nothing looking like an integer after the `-j' option,
there is no limit on the number of job slots. The default number of job
slots is one, which means serial execution (one thing at a time).

One unpleasant consequence of running several commands
simultaneously is that output generated by the commands appears
whenever each command sends it, so messages from different commands may
be interspersed.

Another problem is that two processes cannot both take input from the
same device; so to make sure that only one command tries to take input
from the terminal at once, `make' will invalidate the standard input
streams of all but one running command. This means that attempting to
read from standard input will usually be a fatal error (a `Broken pipe'
signal) for most child processes if there are several.

It is unpredictable which command will have a valid standard input
stream (which will come from the terminal, or wherever you redirect the
standard input of `make'). The first command run will always get it
first, and the first command started after that one finishes will get
it next, and so on.

We will change how this aspect of `make' works if we find a better
alternative. In the mean time, you should not rely on any command using
standard input at all if you are using the parallel execution feature;
but if you are not using this feature, then standard input works
normally in all commands.

Finally, handling recursive `make' invocations raises issues. For
more information on this, see *Note Communicating Options to a
Sub-`make': Options/Recursion.

If a command fails (is killed by a signal or exits with a nonzero
status), and errors are not ignored for that command (*note Errors in
Commands: Errors.), the remaining command lines to remake the same
target will not be run. If a command fails and the `-k' or
`--keep-going' option was not given (*note Summary of Options: Options
Summary.), `make' aborts execution. If make terminates for any reason
(including a signal) with child processes running, it waits for them to
finish before actually exiting.

When the system is heavily loaded, you will probably want to run
fewer jobs than when it is lightly loaded. You can use the `-l' option
to tell `make' to limit the number of jobs to run at once, based on the
load average. The `-l' or `--max-load' option is followed by a
floating-point number. For example,

-l 2.5

will not let `make' start more than one job if the load average is
above 2.5. The `-l' option with no following number removes the load
limit, if one was given with a previous `-l' option.

More precisely, when `make' goes to start up a job, and it already
has at least one job running, it checks the current load average; if it
is not lower than the limit given with `-l', `make' waits until the load
average goes below that limit, or until all the other jobs finish.

By default, there is no load limit.

File: make.info, Node: Errors, Next: Interrupts, Prev: Parallel, Up: Commands

Errors in Commands
==================

After each shell command returns, `make' looks at its exit status.
If the command completed successfully, the next command line is executed
in a new shell; after the last command line is finished, the rule is
finished.

If there is an error (the exit status is nonzero), `make' gives up on
the current rule, and perhaps on all rules.

Sometimes the failure of a certain command does not indicate a
problem. For example, you may use the `mkdir' command to ensure that a
directory exists. If the directory already exists, `mkdir' will report
an error, but you probably want `make' to continue regardless.

To ignore errors in a command line, write a `-' at the beginning of
the line's text (after the initial tab). The `-' is discarded before
the command is passed to the shell for execution.

For example,

clean:
-rm -f *.o

This causes `rm' to continue even if it is unable to remove a file.

When you run `make' with the `-i' or `--ignore-errors' flag, errors
are ignored in all commands of all rules. A rule in the makefile for
the special target `.IGNORE' has the same effect, if there are no
prerequisites. These ways of ignoring errors are obsolete because `-'
is more flexible.

When errors are to be ignored, because of either a `-' or the `-i'
flag, `make' treats an error return just like success, except that it
prints out a message that tells you the status code the command exited
with, and says that the error has been ignored.

When an error happens that `make' has not been told to ignore, it
implies that the current target cannot be correctly remade, and neither
can any other that depends on it either directly or indirectly. No
further commands will be executed for these targets, since their
preconditions have not been achieved.

Normally `make' gives up immediately in this circumstance, returning
a nonzero status. However, if the `-k' or `--keep-going' flag is
specified, `make' continues to consider the other prerequisites of the
pending targets, remaking them if necessary, before it gives up and
returns nonzero status. For example, after an error in compiling one
object file, `make -k' will continue compiling other object files even
though it already knows that linking them will be impossible. *Note
Summary of Options: Options Summary.

The usual behavior assumes that your purpose is to get the specified
targets up to date; once `make' learns that this is impossible, it
might as well report the failure immediately. The `-k' option says
that the real purpose is to test as many of the changes made in the
program as possible, perhaps to find several independent problems so
that you can correct them all before the next attempt to compile. This
is why Emacs' `compile' command passes the `-k' flag by default.

Usually when a command fails, if it has changed the target file at
all, the file is corrupted and cannot be used--or at least it is not
completely updated. Yet the file's time stamp says that it is now up to
date, so the next time `make' runs, it will not try to update that
file. The situation is just the same as when the command is killed by a
signal; *note Interrupts::. So generally the right thing to do is to
delete the target file if the command fails after beginning to change
the file. `make' will do this if `.DELETE_ON_ERROR' appears as a
target. This is almost always what you want `make' to do, but it is
not historical practice; so for compatibility, you must explicitly
request it.

File: make.info, Node: Interrupts, Next: Recursion, Prev: Errors, Up: Commands

Interrupting or Killing `make'
==============================

If `make' gets a fatal signal while a command is executing, it may
delete the target file that the command was supposed to update. This is
done if the target file's last-modification time has changed since
`make' first checked it.

The purpose of deleting the target is to make sure that it is remade
from scratch when `make' is next run. Why is this? Suppose you type
`Ctrl-c' while a compiler is running, and it has begun to write an
object file `foo.o'. The `Ctrl-c' kills the compiler, resulting in an
incomplete file whose last-modification time is newer than the source
file `foo.c'. But `make' also receives the `Ctrl-c' signal and deletes
this incomplete file. If `make' did not do this, the next invocation
of `make' would think that `foo.o' did not require updating--resulting
in a strange error message from the linker when it tries to link an
object file half of which is missing.

You can prevent the deletion of a target file in this way by making
the special target `.PRECIOUS' depend on it. Before remaking a target,
`make' checks to see whether it appears on the prerequisites of
`.PRECIOUS', and thereby decides whether the target should be deleted
if a signal happens. Some reasons why you might do this are that the
target is updated in some atomic fashion, or exists only to record a
modification-time (its contents do not matter), or must exist at all
times to prevent other sorts of trouble.

File: make.info, Node: Recursion, Next: Sequences, Prev: Interrupts, Up: Commands

Recursive Use of `make'
=======================

Recursive use of `make' means using `make' as a command in a
makefile. This technique is useful when you want separate makefiles for
various subsystems that compose a larger system. For example, suppose
you have a subdirectory `subdir' which has its own makefile, and you
would like the containing directory's makefile to run `make' on the
subdirectory. You can do it by writing this:

subsystem:
cd subdir && $(MAKE)

or, equivalently, this (*note Summary of Options: Options Summary.):

subsystem:
$(MAKE) -C subdir

You can write recursive `make' commands just by copying this example,
but there are many things to know about how they work and why, and about
how the sub-`make' relates to the top-level `make'. You may also find
it useful to declare targets that invoke recursive `make' commands as
`.PHONY' (for more discussion on when this is useful, see *Note Phony
Targets::).

For your convenience, GNU `make' sets the variable `CURDIR' to the
pathname of the current working directory for you. If `-C' is